Many electronic components, such as processing units, and radio frequency (RF) devices, are commonly used in many of today's circuits and generate significant amounts of heat. For example, RF devices, such as high electron mobility transistors (HEMTs), are commonly used in radar (aircraft surveillance, weather surveillance, tactical); electronic warfare (EW), including jamming; RF communication systems; and other applications. Processing units, such as CPUs, are commonly used in computers, laptops, mobile electronics, and other applications.
A limiting factor in many of these applications is the maximum component temperature of the heat generating device. Component lifetime is a function of maximum temperature, and as such, a trade-off is often made between lifetime, maximum power output, and/or duty cycle.
The maximum component temperature in these heat generating devices is governed by heat transfer at several layers.
First, the conductive thermal resistance through the heat generating component itself is a factor in determining the maximum component temperature. The electrically active region of a heat generating device is typically located on one side of a semiconductor substrate, which may be, for example, silicon, gallium nitride, or gallium arsenide. This is the region where waste heat is generated. This heat must be conducted through the substrate before being dissipated through the thermal management system.
Second, the heat transfer from the surface of the semiconductor substrate to the thermal management system is a factor in determining the maximum component temperature. Thermal management systems usually conduct heat from the heat generating device into a spreader or heat sink. These systems then dissipate the heat to the ambient environment, such as via free convection, conduction, or radiation, or to a coolant, using forced convection.
For many of these thermal management systems, including forced convection cooling, the size, weight, and power (SWaP) of existing thermal management solutions often drives the design, ultimately limiting their performance. In some embodiments, this challenge is exacerbated by the need to cool an array of heat generating components. For example, a printed circuit board may contain a plurality of heat generating components that are arranged as a matrix on the board. This configuration presents a number of challenges.
First, many existing implementations of fluid cooling at the device level have a defined fluid inlet (cool supply) and fluid outlet (warm exhaust). To provide the greatest cooling to all devices in an array, the inlet for each device must be kept at the lowest possible temperature. When devices are arranged in an array, the inlet fluid from device to device can vary. For example, if device fluid paths are daisy-chained to minimize the number of fluid lines, then the warm exhaust of one device becomes the cool supply for the next. This degrades the thermal performance as more devices are added to the array, and leads to poor temperature uniformity across the array.
Second, the parasitic losses between the cool supply fluid and warm exhaust fluid degrade performance for all devices in an array. Even with single devices, the mere proximity of cool supply fluid and warm exhaust fluid produces parasitic losses whereby the warm exhaust fluid will warm the cool supply fluid. This is particularly exacerbated in arrays where many fluid channels are likely to be in close proximity. These parasitic losses inhibit an arrayed system from reaching maximum performance.
Third, arrays of individually fluid-cooled devices impede panel modularity. Arrays of devices, each with their own cooling, can become inordinately complex for system integration. For example, an 8×8 array would have over 100 fluid lines if they are all plumbed individually.
Therefore, it would be beneficial if there were a thermal management system that addressed these challenges by providing an array backframe with integral manifolding for high performance fluid cooling of devices.